Color video signals, so-called composite video, blanking and sync signals (CVBS), are essentially composed of a brightness signal or a luminance component (Y), two color difference signals or chrominance components (U, V or I, Q), vertical and horizontal sync signals (VS, HS) and a blanking signal (BL). The structure of a composite video signal (CVBS) and the corresponding Y, U and V signals are shown in FIG. 1.
FIG. 1a shows a composite video signal for an EBU (European Broadcasting Union) color bar test signal, with the six hue (tint) values belonging to the vertical color bar being additively superimposed in "carrier packets" with color carrier frequency on the luminance component Y. For color carrier generation, a color subcarrier frequency sync pulse, the burst, is transmitted directly behind the line sync pulse, SYNC. The burst phase and the burst amplitude serve as reference values for determining the hue and color saturation of the demodulated signal, which is represented by the individual carrier packets.
The different coding processes NTSC, PAL and SECAM introduced in the known color television standards, differ in the manner of chrominance transmission and in particular the different systems use different color subcarrier frequencies and different line frequencies.
In digital video signal processing and decoding the prior art fundamentally distinguishes between two system architectures. These are the burst-locked architecture and the line-locked architecture; i.e., systems which in each case operate with sampling frequencies for the video signal, which are produced in phase-locked manner to the color subcarrier frequency transmitted with the burst pulse or in phase-locked manner with the line frequency, respectively.
In the case of decoders with a burst-locked architecture, the sampling frequency is chosen in such a way that on the one hand, it is not too high so as to keep the power losses low, and on the other hand, it fulfills the Nyquist theorem; i.e., f.sub.a &gt;2.multidot.fsc (sampling frequency&gt;2.multidot.chrominance subcarrier frequency). For a problem-free processing of the modulated color carrier in the decoder, it is appropriate to have a sampling frequency, which corresponds to an even multiple of the color subcarrier.
For line-locked architectures, the clock of the digital system is derived from the line frequency and is an integral multiple of the line frequency, so that an integral number of pixels are produced per line.
Although the burst-locked system has advantages with respect to the minimum effort and expenditure for color decoding, from other standpoints, this system has important disadvantages; e.g., in the case of horizontal and vertical synchronization, as well as in multistandard and "non-standard" uses. As the sampling process is essentially non-orthogonal, the burst-locked system is only suitable for the direct representation of images on a screen, but not for producing data for fixed raster applications; e.g., for field or frame stores or for frame grabbers in a PC environment.
Line-locked systems are admittedly suitable for frame, line and field storage purposes, as well as for digital video image processing in multistandard operation, but they give rise to new problems. In particular, much more complex color decoders are required, the analog clock generation requires high circuitry expenditure and the requirements regarding the maximum acceptable dynamic non-linearities of the A/D converter and the preceding analog signal processing stages are very high.
In the case of the prior art digital video signal decoders, no matter whether they operate according to the burst-locked or line-locked principle, the functional elements of the block circuit diagram of the decoder, such as the separating circuit for the luminance/chrominance signal, band-pass filters, control and setting elements and FM demodulators for the color difference signals are realized in separate functional blocks and are also found again in this form. Account is taken of the fact that redundancies occur with respect to similar tasks for the same partial functions by essentially directly converting the block circuit diagram.
Signal processing takes place either directly in the time or pixel domain or following a corresponding transformation of the digitized video signal in the frequency domain, the decoded signal then being transformed back into the time or pixel domain. For transforming the video signal from the pixel domain into the frequency domain, in the case of prior art digital decoders use is generally made of Fourier transformation or discrete cosine transformation, the latter having the advantage that it requires fewer multipliers than Fourier transformation. Up to now, the realization of such digital video signal decoders has involved a relatively high circuit expenditure. In particular, the multipliers needed for the transformation increase the costs for producing the digital decoder in an IC to a considerable extent.
The problem of the invention is to provide a decoder for digital video signals and a method for digitally decoding a composite video signal, which can be realized with reduced circuitry and computing expenditure than in the hitherto known decoders and methods.